Array sense amplifiers, memory devices and systems including same, and methods of operation

ABSTRACT

A sense amplifier having an amplifier stage with decreased gain is described. The sense amplifier includes a first input/output (“I/O”) node and a second complementary I/O node. The sense amplifier includes two amplifier stages, each for amplifying a signal on one of the I/O nodes. The first amplifier stage, having a first conductivity-type, amplifies one of the I/O node towards a first voltage. The second amplifier stage, having a second conductivity-type, amplifies the other I/O node towards a second voltage. The sense amplifier also includes a resistance circuit coupled to the second amplifier stage to reduce the gain of the second amplifier stage thereby reducing the rate of amplification of the signal on the corresponding I/O node.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of U.S. patent application Ser. No.11/646,735, filed Dec. 27, 2006. This application is incorporated byreference herein.

TECHNICAL FIELD

This invention, in various embodiments, relates generally to integratedcircuits and, more specifically, to array sense amplifiers in memorydevices.

BACKGROUND OF THE INVENTION

Memory devices, such as static random access memory (“SRAM”) devices anddynamic random access memory (“DRAM”) devices are in common use in awide variety of electronic systems, such as personal computers. Memorydevices include one or more arrays of memory cells, which in DRAMdevices, are small capacitors that are arranged in rows and columns.Data is represented by the presence or absence of a charge on thecapacitor in the memory cell. Data can be stored in the memory cellsduring a write operation or retrieved from the memory cells during aread operation. If the capacitor in the addressed or selected memorycell is charged, then the capacitor discharges onto a digit lineassociated with the memory cell, which causes a change in the voltage onthe digit line. On the other hand, if the capacitor in the selectedmemory cell is not charged, then the voltage on the digit lineassociated with the memory cell remains constant. The change in voltage(or lack of change) on the digit line can be detected to determine thestate of the capacitor in the selected memory cell, which indicates thevalue of the data bit stored in the memory cell.

Sense amplifiers are used to improve the accuracy of determining thestate of the capacitor in selected memory cells. As known in the art,when the memory cell array is accessed, a row of memory cells areactivated, and the sense amplifiers amplify data for the respectivecolumn of memory cells by coupling each of the digit lines of theselected column to voltage supplies such that the digit lines havecomplementary logic levels. A conventional sense amplifier 100 of a DRAMmemory array is shown in FIG. 1. The sense amplifier 100 is coupled to apair of complementary digit lines DIGIT and DIGIT_ to which a largenumber of memory cells (not shown) are connected. The sense amplifier100 includes a pair of cross-coupled PMOS transistors 102, 104. Thesources of the PMOS transistors 102, 104 share a common node to which aPMOS activation signal ACT is coupled during operation. The ACT signalis typically provided by a power supply voltage (not shown) duringoperation. The sense amplifier 100 also includes a pair of cross-coupledNMOS transistors 112, 114. The drains of the NMOS transistors 112, 114also share a common node to which an NMOS activation signal RNL_ iscoupled during operation. The RNL_ signal is typically provided by beingconnected to ground (not shown) during operation. The sense amplifier100 is configured as a pair of cross-coupled inverters in which the ACTand RNL_ signals provide power and ground, respectively. The digit linesDIGIT and DIGIT_ are additionally coupled together by an equilibrationtransistor 110 having a gate coupled to receive a control signal EQ.

In operation, the sense amplifier 100 equilibrates the digit lines DIGITand DIGIT_, senses a differential voltage that develops between thedigit lines DIGIT and DIGIT_, and then drives the digit lines tocorresponding logic levels. In response to an active HIGH EQ signal theequilibration transistor 110 turns ON, connecting the digit lines DIGITand DIGIT_ to each other and equilibrating the digit lines to the samevoltage. The digit lines are typically equilibrated to V_(CC)/2, whichkeeps the PMOS transistors 102, 104 and the NMOS transistors 112, 114turned OFF. After the differential voltage between the digit lines DIGITand DIGIT_ has reached substantially zero volts, the EQ signaltransitions LOW to turn OFF the transistor 110.

When a memory cell is accessed, the voltage of one of the digit linesDIGIT or DIGIT_ increases slightly, resulting in a voltage differentialbetween the digit lines. While one digit line contains a charge from theaccessed cell, the other digit line does not and serves as a referencefor the sensing operation. Assuming, for example, the voltage on theDIGIT line increases, the voltage level of the DIGIT line increasesslightly above V_(CC)/2 causing the gate-to-source voltage of the NMOStransistor 114 to be greater than the NMOS transistor 112. The RNLsignal is activated, driving the common node of the NMOS transistors112, 114 to ground, switching the NMOS transistor 114 ON. As a result,the complementary digit line DIGIT_ is coupled to the active RNL_ signaland is pulled to ground. In response to the low voltage level of theDIGIT_ line, the gate-to-source voltage of the PMOS transistor 102increases, and in response to activation of the ACT signal, is turned ONdue to the gate-to-source voltage being larger than the PMOS transistor104. The DIGIT line is consequently coupled to the power supply voltageas provided by the active ACT signal, and the PMOS transistor 102 drivesthe digit line DIGIT towards the power supply voltage. Thereafter, thevoltage on the digit line DIGIT further increases and the voltage on thecomplementary digit line DIGIT_ further decreases. At the end of thesensing period, the NMOS transistor 114 has driven complementary digitline DIGIT_ to ground by the active RNL_ signal and the PMOS transistor102 has driven the digit line DIGIT to the power supply voltage V_(CC)by the active ACT signal.

Random threshold voltage mismatch of transistor components inconventional sense amplifiers 100 are undesirable because deviations ofthe threshold voltage may abruptly cause an imbalance in the senseamplifier that can erroneously amplify input signals in the wrongdirection. For example, the offset due to a threshold voltage mismatchof the sense amplifier 100 may be amplified by the large gain of theNMOS transistors 112, 114, as will be understood by one skilled in theart. Consequently, the sense amplifier 100 would likely amplify thesignal on the asserted digit line incorrectly, resulting in reading theincorrect data. Errors and delays due to mismatched threshold voltagesin sense amplifiers ultimately affect the overall accuracy of memoryoperations. While efforts have been made to compensate for thresholdvoltage offsets, such compensation methods typically increase memoryaccess time, occupy chip space and increase power consumption.

Therefore, there is a need for a sense amplifier designed to havetolerance to voltage threshold mismatch of transistor componentsincluded in the sense amplifier.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic drawing of a conventional sense amplifier.

FIG. 2 is a schematic drawing of a sense amplifier according to anembodiment of the invention.

FIG. 3 is a schematic drawing of a sense amplifier according to anotherembodiment of the invention.

FIG. 4 is a schematic drawing of a sense amplifier according to anotherembodiment of the invention.

FIG. 5 is a functional block diagram of a memory device including asense amplifier according to an embodiment of the invention.

FIG. 6 is a functional block diagram of a computer system including thememory device of FIG. 5.

DETAILED DESCRIPTION

Certain details are set forth below to provide a sufficientunderstanding of the invention. However, it will be clear to one skilledin the art that the invention may be practiced without these particulardetails. In other instances, well-known circuits, control signals, andtiming protocols have not been shown in detail in order to avoidunnecessarily obscuring the invention.

FIG. 2 illustrates a sense amplifier 200 according to an embodiment ofthe invention. Components and signals that were previously describedwith reference to FIG. 1 have been given the same reference numbers inFIG. 2. The sense amplifier 200 of FIG. 2 includes an NMOS amplifierstage 201 having a pair of NMOS transistors 222, 224 coupled to thesources of the NMOS transistors 112, 114 to provide source degeneration.The drains to each of the NMOS transistors 222, 224 are coupled to thesources of the NMOS transistors 112, 114, and the sources of the NMOStransistors 222, 224 are coupled to a common node coupled to ground. Thegates of the NMOS transistors 222, 224 are coupled together and receivea control signal SLAT that provides a voltage signal to the respectivegates. In the source degenerate configuration, the NMOS transistors 222,224 provide a resistance on the sources of the NMOS transistors 112,114. The effect of adding resistance at the NMOS amplifier stage 201reduces the gain of the NMOS transistors 112, 114. As a result, anoffset that typically would have been amplified due to a thresholdvoltage mismatch is reduced, which in turn minimizes its interferencewith amplifying the digit line signal. The resistance provided by theNMOS transistors 222, 224 may be changed by adjusting the voltage of theSLAT signal. The SLAT signal may be predetermined for the senseamplifier 200 by design or be an adjustable control signal by a user.

In operation, the DIGIT and DIGIT_ lines are precharged to Vcc/2 and thevoltages of the digit lines are equilibrated by activating the EQ signaland coupling the two digit lines together through the transistor 110.The EQ signal is then deactivated to isolate the DIGIT and DIGIT_ linesin preparation for a sense operation. A word line (not shown) of thememory cell array is activated to couple a row of memory cells to arespective digit line and to a respective sense amplifier 200. Aspreviously described, coupling a memory cell to the respective digitline causes a voltage differential between the DIGIT and DIGIT_ lines.In the present example, it will be assumed that the accessed memory cellis coupled to the DIGIT line and increases the voltage to slightly aboveVcc/2. As a result, the gate-to-source voltage of the NMOS transistor114 is greater than for the NMOS transistor 112.

Prior to activation of the RNL_ and ACT signals, the SLAT signal isactivated to couple the sources of the transistors 112, 114 to a commonnode 226 through the transistors 222, 224. As a result, voltage of boththe DIGIT and DIGIT_ lines slightly decrease. With the greatergate-to-source voltage for the NMOS transistor 114, the voltage of theDIGIT_ line is discharged more quickly to the common node 226 than forthe DIGIT line, resulting in the PMOS transistor 102 having a greatergate-to-source voltage than for the PMOS transistor 104. The ACT signalis then activated (typically providing Vcc, a power supply voltage), anddue to the greater gate-to-source voltage of the PMOS transistor 102,the transistor 102 begins to switch ON before the PMOS transistor 104,further increasing the gate-to-source voltage of the NMOS transistor114. The RNL_ signal is activated coupling the sources of the NMOStransistors 112, 114 to ground, fully switching ON the transistor 114and fully coupling the DIGIT_ line to ground. The PMOS transistor 102 isconsequently fully switching ON by the grounded DIGIT_ line and fullycouples the DIGIT line to Vcc, latching the DIGIT and DIGIT_ lines torespective voltages Vcc and ground.

As previously discussed, the transistors 222, 224 increase thesource-to-ground resistance of the NMOS transistors 112, 114 to providesource degeneration and reduce the gain of the NMOS transistors 112,114. The trade-off for reducing the gain of the NMOS transistors 112,114 is that the current gain is also reduced, which slows theamplification of the DIGIT and DIGIT_ lines. The slower amplification ofthe NMOS amplifier stage 201 allows time for the PMOS transistors 102,104 to recover towards Vcc before the NMOS transistors 112, 114 arefully driven to ground. As a result, failure to pull-up the voltage ofone of the digit lines due to transistor threshold voltage mismatch isreduced during normal operation of the sense amplifier 200.

FIG. 3 illustrates a sense amplifier 300 according to another embodimentof the invention. The sense amplifier 300 is similar to the senseamplifier 200 previously described with reference to FIG. 2. Thetransistors 222, 224 of the sense amplifier 200, however, have beenreplaced in the sense amplifier 300 with resistors 322, 324. Aspreviously discussed, the transistors 222, 224 increased thesource-to-ground resistance of the NMOS transistors 112, 114 to providesource degeneration. The resistors 322, 324 are used to provideincreased source-to-ground resistance in place of the transistors 222,224. Operation of the sense amplifier 300 is the same as for the senseamplifier 200 except that provision of an active SLAT signal is notnecessary.

FIG. 4 illustrates a sense amplifier 400 according to another embodimentof the invention. The sense amplifier 400 is similar to the senseamplifier 200 previously described with reference to FIG. 2. However,additional NMOS transistors 216, 218 are included in the sense amplifier400 and the common node 226 is coupled to ground. The NMOS transistors216, 218 are used to enhance pull-down of the DIGIT and DIGIT_ lines toground during sensing. The drains of the NMOS transistors 216, 218 arecoupled to the respective drains of the NMOS transistors 112, 114, andthe gates of the NMOS transistors 216, 218 are also respectively coupledto the gates of the NMOS transistors 112, 114. The sources of the NMOStransistors 216, 218 are coupled together and share a common node towhich the RNL_ signal is coupled.

Operation of the sense amplifier 400 is similar to operation of thesense amplifier 200. The increase of gate-to-source voltage of one ofthe NMOS transistors 112, 114 in response to coupling a memory cell toeither the DIGIT or DIGIT_ line also increases the gate-to-sourcevoltage of one of the NMOS transistors 216, 218. With the common node226 coupled to ground, rather than to receive the RNL_ signal, thevoltage of the DIGIT and DIGIT_ lines begin to discharge to groundimmediately rather than waiting for the RNL_ signal to become active. Aspreviously discussed with reference to the sense amplifier 200, thedecreasing voltage of the DIGIT or DIGIT_ line creates a gate-to-sourcevoltage imbalance between the PMOS transistors 102, 104, with one of thetwo transistors switching ON before the other in response to the ACTsignal becoming active. In addition to causing either of the NMOStransistors 112, 114 to switch ON more fully, the corresponding NMOStransistors 216, 218 is more fully switched ON as well. In response tothe RNL_ signal becoming active, the conductive NMOS transistor 216 or218 provides additional drive capability to pull-down the DIGIT orDIGIT_ line to ground more quickly than compared to the sense amplifier200.

In another embodiment, the sense amplifier 300 of FIG. 3 is modified toincludes additional transistors to provide greater drive capability topull-down the DIGIT or DIGIT_ line, as previously discussed withreference to the sense amplifier 400 of FIG. 4. Resistors, multipletransistors, impedances sources or any other components, or combinationsthereof may be used in place of the NMOS transistors 222, 224, as isknown in the art, to provide source degeneration and reduce the gain ofthe NMOS transistors 1112, 114.

The sense amplifiers 200, 300, and 400 were previously described inoperation according to a particular activation sequence of signals, forexample, the EQ, SLAT, ACT, and RNL_ signals. In other embodiments ofthe invention, the activation sequence of signals is different than thatpreviously described. Those ordinarily skilled in the art will obtainsufficient understanding from the description provided herein to makesuch modifications to practice these other embodiments. The presentinvention is not limited to the particular sequence previously describedfor the previously described embodiments of the invention.

FIG. 5 illustrates an embodiment of a memory device 500 including atleast one sense amplifier according to an embodiment of the presentinvention. The memory device 500 includes an address register 502 thatreceives row, column, and bank addresses over an address bus ADDR, witha memory controller (not shown) typically supplying the addresses. Theaddress register 502 receives a row address and a bank address that areapplied to a row address multiplexer 504 and bank control logic circuit506, respectively. The row address multiplexer 504 applies either therow address received from the address register 502 or a refresh rowaddress from a refresh counter 508 to a plurality of row address latchand decoders 510A-D. The bank control logic 506 activates the rowaddress latch and decoder 510A-D corresponding to either the bankaddress received from the address register 502 or a refresh bank addressfrom the refresh counter 508, and the activated row address latch anddecoder latches and decodes the received row address.

In response to the decoded row address, the activated row address latchand decoder 510A-D applies various signals to a corresponding memorybank 512A-D, including a row activation signal to activate a row ofmemory cells corresponding to the decoded row address. Each memory bank512A-D includes a memory-cell array having a plurality of memory cellsarranged in rows and columns. Data stored in the memory cells in theactivated row are sensed and amplified by sense amplifiers 511 in thecorresponding memory bank. The sense amplifiers 511 are designedaccording to an embodiment of the present invention. The row addressmultiplexer 504 applies the refresh row address from the refresh counter508 to the decoders 510A-D and the bank control logic circuit 506 usesthe refresh bank address from the refresh counter when the memory device500 operates in an auto-refresh or self-refresh mode of operation inresponse to an auto- or self-refresh command being applied to the memorydevice 500, as will be appreciated by those skilled in the art.

A column address is applied on the ADDR bus after the row and bankaddresses, and the address register 502 applies the column address to acolumn address counter and latch 514 which, in turn, latches the columnaddress and applies the latched column address to a plurality of columndecoders 516A-D. The bank control logic 506 activates the column decoder516A-D corresponding to the received bank address, and the activatedcolumn decoder decodes the applied column address. Depending on theoperating mode of the memory device 500, the column address counter andlatch 514 either directly applies the latched column address to thedecoders 516A-D, or applies a sequence of column addresses to thedecoders starting at the column address provided by the address register502. In response to the column address from the counter and latch 514,the activated column decoder 516A-D applies decode and control signalsto an I/O gating and data masking circuit 518 which, in turn, accessesmemory cells corresponding to the decoded column address in theactivated row of memory cells in the memory bank 512A-D being accessed.

During data read operations, data being read from the addressed memorycells is coupled through the I/O gating and data masking circuit 518 toa read latch 520. The I/O gating and data masking circuit 518 supplies Nbits of data to the read latch 520, which then applies two N/2 bit wordsto a multiplexer 522. In the embodiment of FIG. 3, the circuit 518provides 64 bits to the read latch 520 which, in turn, provides two 32bits words to the multiplexer 522. A data driver 524 sequentiallyreceives the N/2 bit words from the multiplexer 522 and also receives adata strobe signal DQS from a strobe signal generator 526. The DQSsignal is used by an external circuit such as a memory controller (notshown) in latching data from the memory device 500 during readoperations. The data driver 524 sequentially outputs the received N/2bits words as a corresponding data word DQ, each data word being outputin synchronism with a rising or falling edge of a CLK signal that isapplied to clock the memory device 500. The data driver 524 also outputsthe data strobe signal DQS having rising and falling edges insynchronism with rising and falling edges of the CLK signal,respectively. Each data word DQ and the data strobe signal DQScollectively define a data bus DATA.

During data write operations, an external circuit such as a memorycontroller (not shown) applies N/2 bit data words DQ, the strobe signalDQS, and corresponding data masking signals DM on the data bus DATA. Adata receiver 528 receives each DQ word and the associated DM signals,and applies these signals to input registers 530 that are clocked by theDQS signal. In response to a rising edge of the DQS signal, the inputregisters 530 latch a first N/2 bit DQ word and the associated DMsignals, and in response to a falling edge of the DQS signal the inputregisters latch the second N/2 bit DQ word and associated DM signals.The input register 530 provides the two latched N/2 bit DQ words as anN-bit word to a write FIFO and driver 532, which clocks the applied DQword and DM signals into the write FIFO and driver in response to theDQS signal. The DQ word is clocked out of the write FIFO and driver 532in response to the CLK signal, and is applied to the I/O gating andmasking circuit 518. The I/O gating and masking circuit 518 transfersthe DQ word to the addressed memory cells in the accessed bank 512A-Dsubject to the DM signals, which may be used to selectively mask bits orgroups of bits in the DQ words (i.e., in the write data) being writtento the addressed memory cells.

A control logic and command decoder 534 receives a plurality of commandand clocking signals over a control bus CONT, typically from an externalcircuit such as a memory controller (not shown). The command signalsinclude a chip select signal CS*, a write enable signal WE*, a columnaddress strobe signal CAS*, and a row address strobe signal RAS*, whilethe clocking signals include a clock enable signal CKE* andcomplementary clock signals CLK, CLK*, with the “*” designating a signalas being active low. The command signals CS*, WE*, CAS*, and RAS* aredriven to values corresponding to a particular command, such as a read,write, or auto-refresh command. In response to the clock signals CLK,CLK*, the command decoder 534 latches and decodes an applied command,and generates a sequence of clocking and control signals that controlthe components 502-532 to execute the function of the applied command.The clock enable signal CKE enables clocking of the command decoder 534by the clock signals CLK, CLK*. The command decoder 534 latches commandand address signals at positive edges of the CLK, CLK* signals (i.e.,the crossing point of CLK going high and CLK* going low), while theinput registers 530 and data drivers 524 transfer data into and from,respectively, the memory device 500 in response the data strobe signalDQS. The detailed operation of the control logic and command decoder 534in generating the control and timing signals is conventional, and thus,for the sake of brevity, will not be described in more detail. Althoughpreviously described with respect to a dynamic random access memorydevice, embodiments of the present invention can be utilized inapplications other than for a memory device where it is desirable toreduce the effects a threshold voltage mismatch when the voltage levelof an input signal is amplified.

FIG. 6 is a block diagram of a computer system 600 including computercircuitry 602 including the memory device 500 of FIG. 5. Typically, thecomputer circuitry 602 is coupled through address, data, and controlbuses to the memory device 500 to provide for writing data to andreading data from the memory device. The computer circuitry 602 includescircuitry for performing various computing functions, such as executingspecific software to perform specific calculations or tasks. Inaddition, the computer system 600 includes one or more input devices604, such as a keyboard or a mouse, coupled to the computer circuitry602 to allow an operator to interface with the computer system. Thecomputer system 600 may include one or more output devices 606 coupledto the computer circuitry 602, such as output devices typicallyincluding a printer and a video terminal. One or more data storagedevices 608 may also be coupled to the computer circuitry 602 to storedata or retrieve data from external storage media (not shown). Examplesof typical storage devices 608 include hard and floppy disks, tapecassettes, compact disk read-only (CD-ROMs) and compact disk read-write(CD-RW) memories, and digital video disks (DVDs).

From the foregoing it will be appreciated that, although specificembodiments of the invention have been described herein for purposes ofillustration, various modifications may be made without deviating fromthe spirit and scope of the invention. For example, many of thecomponents described above may be implemented using either digital oranalog circuitry, or a combination of both. Accordingly, the inventionis not limited except as by the appended claims.

1. A sense amplifier comprising: a first input/output (“I/O”) node and asecond I/O node complementary to the first I/O node; a first amplifierstage operable to couple the first I/O node to a first voltage andamplify a first I/O node signal to the first voltage, the firstamplifier stage comprising cross-coupled PMOS transistors; a secondamplifier stage operable to couple the second I/O node to a secondvoltage and amplify a second I/O node signal to the second voltage; anda resistance circuit coupled to the second amplifier stage andconfigured to reduce the gain of the second amplifier stage to slow therate of amplification of the second I/O node signal.
 2. The senseamplifier of claim 1 wherein the resistance circuit comprises tworesistors.
 3. The sense amplifier of claim 1 wherein the first voltagecomprises a power supply voltage and the second voltage comprisesground.
 4. A sense amplifier comprising: a first input/output (“I/O”)node and a second I/O node complementary to the first I/O node; a firstamplifier stage operable to couple the first I/O node to a first voltageand amplify a first I/O node signal to the first voltage, the firstamplifier stage comprising cross-coupled PMOS transistors; a secondamplifier stage operable to couple the second I/O node to a secondvoltage and amplify a second I/O node signal to the second voltage; anda circuit coupled to the second amplifier stage and configured to reducethe gain of the second amplifier stage to slow the rate of amplificationof the second I/O node signal.
 5. The sense amplifier of claim 4 furthercomprising a driver circuit coupled to the second amplifier stage andoperable to increase the drive of the respectively coupled I/O nodetoward the second voltage.
 6. The sense amplifier of claim 5 wherein thedriver circuit further comprises a pair NMOS transistors respectivelycoupled to each of the NMOS transistors of the second amplifier stage.7. The sense amplifier of claim 4 further comprising an equilibriumcircuit coupled to the first and second I/O nodes, and configured toreceive a control signal for precharging the first and second I/O nodesto the same voltage.
 8. The sense amplifier of claim 7 wherein theequilibrium circuit comprises an NMOS transistor.
 9. The sense amplifierof claim 4 wherein the first voltage comprises a power supply voltageand the second voltage comprises ground.
 10. An amplifier for sensing adifferential voltage comprising: a precharge switch coupled to a pair ofoutput terminals and configured to precharge the pair of outputterminals to substantially the same voltage level; a first pair oftransistors cross-coupled to each other and to the pair of outputterminals respectively, each transistor of the first pair operable tocouple one of the pair of output terminals to a first voltage; a secondpair of transistors cross-coupled to each other and to the pair ofoutput terminals respectively, each transistor of the second pairoperable to couple one of the pair of output terminals to a secondvoltage; and a circuit coupled to the second pair of transistors and toa ground source, the circuit configured to reduce the gain of the secondpair of transistors.
 11. The amplifier of claim 10 wherein the secondpair of transistors is configured to amplify a voltage differentialbetween the output terminals.
 12. The amplifier of claim 10 wherein theprecharge switch is further configured to precharge the pair of outputterminals to a voltage level VCC/2.
 13. The amplifier of claim 10wherein the first pair of transistors comprises cross-coupled PMOStransistors.
 14. The amplifier of claim 13 wherein the second pair oftransistors comprises cross-coupled NMOS transistors.
 15. The amplifierof claim 10 wherein the driver circuit further comprises a third pair oftransistors respectively coupled to each of the cross-coupledtransistors of the second pair of transistors.
 16. The amplifier ofclaim 10 further comprising a driver circuit coupled to the second pairof transistors, the driver circuit operable to increase drive of therespectively coupled output terminal towards the second voltage.
 17. Theamplifier of claim 10 wherein the precharge switch comprises an NMOStransistor.
 18. The amplifier of claim 10 wherein the first voltagecomprises VCC and the second voltage comprises ground.
 19. A senseamplifier for sensing a differential voltage between a pair ofcomplementary digit lines comprising: a first sense line and a secondsense line complementary to the first sense line; a precharge transistorcoupled to the first and second sense lines, and further having a gateconfigured to receive a precharge control signal; a first senseamplifier stage comprising a first pair of transistors cross-coupled tothe first and second sense lines respectively, and further being coupledto a first voltage supply, the first pair of transistors beingconfigured to amplify the first sense line towards the first voltagesupply; and a second sense amplifier stage comprising a second pair oftransistors cross-coupled to the first and second sense linesrespectively, and further being coupled to a second voltage supply thatis different from the first voltage supply, the second pair oftransistors being configured to amplify the second sense line towardsthe second voltage supply with a gain that is less than a gain that thefirst pair of transistors are configured to amplify the first sense linetowards the first voltage supply.
 20. The sense amplifier of claim 19wherein the first voltage supply comprises VCC and the second voltagesupply comprises ground.
 21. The sense amplifier of claim 20 wherein theNMOS transistor is configured to equilibrate the first and second senselines to VCC/2.
 22. The sense amplifier of claim 19 wherein the firstpair of transistors comprise a pair of PMOS transistors, and the secondpair of transistors comprise a pair of NMOS transistors.
 23. A senseamplifier for sensing a differential voltage between a pair ofcomplementary digit lines comprising: a first sense line and a secondsense line complementary to the first sense line; a precharge transistorcoupled to the first and second sense lines, and further having a gateconfigured to receive a precharge control signal; a first senseamplifier stage comprising a first pair of transistors cross-coupled tothe first and second sense lines respectively, and further being coupledto a first voltage supply, the first pair of transistors beingconfigured to amplify the first sense line towards the first voltagesupply; and a second sense amplifier stage comprising a second pair oftransistors cross-coupled to the first and second sense linesrespectively, and further being coupled to a second voltage supply thatis different from the first voltage supply, the second pair oftransistors being configured to amplify the second sense line towardsthe second voltage supply more slowly that the first pair of transistorsamplify the first sense line towards the first voltage supply.
 24. Thesense amplifier of claim 23 wherein the first voltage supply comprisesVCC and the second voltage supply comprises ground.
 25. The senseamplifier of claim 24 wherein the NMOS transistor is configured toequilibrate the first and second sense lines to VCC/2.
 26. The senseamplifier of claim 23 wherein the first pair of transistors comprise apair of PMOS transistors, and the second pair of transistors comprise apair of NMOS transistors.
 27. A sense amplifier comprising: a firstinput/output (“I/O”) node and a second I/O node complementary to thefirst I/O node; a first amplifier stage operable to couple the first I/Onode to a first voltage and amplify a first I/O node signal to the firstvoltage, the first amplifier stage comprising cross-coupled NMOStransistors; a second amplifier stage operable to couple the second I/Onode to a second voltage and amplify a second I/O node signal to thesecond voltage; and a resistance circuit coupled to the second amplifierstage and configured to reduce the gain of the second amplifier stage toslow the rate of amplification of the second I/O node signal.
 28. Thesense amplifier of claim 27 wherein the resistance circuit comprises tworesistors.
 29. A sense amplifier comprising: a first input/output(“I/O”) node and a second I/O node complementary to the first I/O node;a first amplifier stage operable to couple the first I/O node to a firstvoltage and amplify a first I/O node signal to the first voltage, thefirst amplifier stage comprising cross-coupled NMOS transistors; asecond amplifier stage operable to couple the second I/O node to asecond voltage and amplify a second I/O node signal to the secondvoltage; and a circuit coupled to the second amplifier stage andconfigured to reduce the gain of the second amplifier stage to slow therate of amplification of the second I/O node signal.
 30. The senseamplifier of claim 29 further comprising a driver circuit coupled to thesecond amplifier stage and operable to increase the drive of therespectively coupled I/O node toward the second voltage.
 31. The senseamplifier of claim 30 wherein the driver circuit further comprises apair NMOS transistors respectively coupled to each of the NMOStransistors of the second amplifier stage.
 32. The sense amplifier ofclaim 29 further comprising an equilibrium circuit coupled to the firstand second I/O nodes, and configured to receive a control signal forprecharging the first and second I/O nodes to the same voltage.
 33. Thesense amplifier of claim 32 wherein the equilibrium circuit comprises anNMOS transistor.
 34. The sense amplifier of claim 29 wherein the firstvoltage comprises a power supply voltage and the second voltagecomprises ground.
 35. A sense amplifier comprising: a first input/output(“I/O”) node and a second I/O node complementary to the first I/O node;a first amplifier stage operable to couple the first I/O node to a firstvoltage and amplify a first I/O node signal to the first voltage; asecond amplifier stage operable to couple the second I/O node to asecond voltage and amplify a second I/O node signal to the secondvoltage; a circuit coupled to the second amplifier stage and configuredto reduce the gain of the second amplifier stage to slow the rate ofamplification of the second I/O node signal; and an equilibrium circuitcoupled to the first and second I/O nodes, and configured to receive acontrol signal for precharging the first and second I/O nodes to thesame voltage.
 36. The sense amplifier of claim 35 wherein theequilibrium circuit comprises an NMOS transistor.
 37. The senseamplifier of claim 36 wherein the first voltage comprises a power supplyvoltage and the second voltage comprises ground.
 38. A sense amplifiercomprising: a first input/output (“I/O”) node and a second I/O nodecomplementary to the first I/O node; a first amplifier stage operable tocouple the first I/O node to a power supply voltage and amplify a firstI/O node signal to the power supply voltage; a second amplifier stageoperable to couple the second I/O node to ground voltage and amplify asecond I/O node signal to the ground voltage; and a circuit coupled tothe second amplifier stage and configured to reduce the gain of thesecond amplifier stage to slow the rate of amplification of the secondI/O node signal.